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? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14569b/d mc14569b programmable divide-by-n dual 4-bit binary/bcd down counter the mc14569b is a programmable dividebyn dual 4bit binary or bcd down counter constructed with mos pchannel and nchannel enhancement mode devices (complementary mos) in a monolithic structure. this device has been designed for use with the mc14568b phase comparator/counter in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. ? speedup circuitry for zero detection ? each 4bit counter can divide independently in bcd or binary mode ? can be cascaded with mc14526b for frequency synthesizer applications ? all outputs are buffered ? schmitt triggered clock conditioning maximum ratings (voltages referenced to v ss ) (note 1.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 2.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 1. maximum ratings are those values beyond which damage to the device may occur. 2. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14569bcp pdip16 2000/box mc14569bdt tssop16 96/rail marking diagrams 1 16 pdip16 p suffix case 648 mc14569bcp awlyyww soic16 dw suffix case 751g 1 16 14569b awlyyww mc14569bdw soic16 47/rail mc14569bdwr2 soic16 1000/tape & reel tssop16 dt suffix case 948f 14 569b alyw 1 16
mc14569b http://onsemi.com 2 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 p5 p6 p7 q v dd clock ctl 2 p4 p1 p0 ctl1 zero detect v ss cascade feedback p3 p2 pin assignment block diagram ctl = low for binary count ctl = high for bcd count cascade feedback clock 9 7 v dd = pin 16 v ss = pin 8 15 1 zero detect q clock load zero detect encoder binary/bcd counter #1 binary/bcd counter #2 p0 p1 p2 p3 ctl 1 ctl 2 p4 p5 p6 p7 14 13 12 11 10 2 6 5 4 3
mc14569b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (3.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc v in = 0 or v dd a1o level v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc (v o = 0.5 or 4.5 vdc) a1o level (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (4.) (5.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.58 m a/khz) f + i dd i t = (1.20 m a/khz) f + i dd i t = (1.95 m a/khz) f + i dd m adc 3. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 4. the formulas given are for the typical characteristics only at 25 c. 5. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14569b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics* (c l = 50 pf, t a = 25 c) v dd all types characteristic symbol v dd vdc min typ (6.) max unit output rise time t tlh 5.0 10 15 e e e 100 50 40 200 100 80 ns output fall time t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns turnon delay time zero detect output t plh 5.0 10 15 e e e 420 175 125 700 300 250 ns q output 5.0 10 15 e e e 675 285 200 1200 500 400 ns turnoff delay time zero detect output t phl 5.0 10 15 e e e 380 150 100 600 300 200 ns q output 5.0 10 15 e e e 530 225 155 1000 400 300 ns clock pulse width t wh 5.0 10 15 300 150 115 100 45 30 e e e ns clock pulse frequency f cl 5.0 10 15 e e e 3.5 9.5 13.0 2.1 5.1 7.8 mhz clock pulse rise and fall time t tlh , t thl 5.0 10 15 no limit m s 6. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance.
mc14569b http://onsemi.com 5 switching waveforms t wh figure 1. figure 2. 20 ns 20 ns clock q clock zero detect 90% 50% 10% 50% 90% 10% t plh t phl 20 ns 20 ns 90% 50% 10% t wh t plh t phl 90% 10% t tlh t thl t tlh t thl f in = f max
mc14569b http://onsemi.com 6 pin descriptions inputs p0, p1, p2, p3 (pins 3, 4, 5, 6) e preset inputs. programmable inputs for the least significant counter. may be binary or bcd depending on the control input. p4, p5, p6, p7 (pins 11, 12, 13, 14) e preset inputs. programmable inputs for the most significant counter. may be binary or bcd depending on the control input. clock (pin 9) e preset data is decremented by one on each positive transition of this signal. outputs zero detect (pin 1) e this output is normally low and goes high for one clock cycle when the counter has decremented to zero. q (pin 15) e output of the last stage of the most significant counter. this output will be inactive unless the preset input p7 has been set high. controls cascade feedback (pin 7) e this pin is normally set high. when low, loading of the preset inputs (p0 through p7) is inhibited, i.e., p0 through p7 are adon't cares.o refer to table 1 for output characteristics. ctl 1 (pin 2) e this pin controls the counting mode of the least significant counter. when set high, counting mode is bcd. when set low, counting mode is binary. ctl 2 (pin 10) e this pin controls the counting mode of the most significant counter. when set high, counting mode is bcd. when set low, counting mode is binary. supply pins v ss (pin 18) e negative supply voltage. this pin is usually connected to ground. v dd (pin 16) e positive supply voltage. this pin is connected to a positive supply voltage ranging from 3.0 volts to 18.0 volts. operating characteristics the mc14569b is a programmable dividebyn dual 4bit down counter. this counter may be programmed (i.e., preset) in bcd or binary code through inputs p0 to p7. for each counter, the counting sequence may be chosen independently by applying a high (for bcd count) or a low (for binary count) to the control inputs ctl 1 and ctl 2 . the divide ratio n (n being the value programmed on the preset inputs p0 to p7) is automatically loaded into the counter as soon as the count 1 is detected. therefore, a division ratio of one is not possible. after n clock cycles, one pulse appears on the zero detect output. (see timing diagram.) the q output is the output of the last stage of the most significant counter (see tables 1 through 5, mode controls.) when cascading the mc14569b to the mc14526b, the cascade feedback input, q, and zero detect outputs must be respectively connected to a0o, clock, and load of the following counter. if the mc14569b is used alone, cascade feedback must be connected to v dd . 18 16 14 12 10 8.0 6.0 4.0 2.0 0 +100 +80 +60 +40 +20 0 -20 -40 t a , ambient temperature ( c) f, frequency (mhz), typical c l = 50 pf v dd = 15 v 10 v 5.0 v
mc14569b http://onsemi.com 7 table 1. mode controls (cascade feedback = low) counter control values divide ratio ctl 1 ctl 2 zero detect q 0 0 256 256 0 1 160 160 1 0 160 160 1 1 100 100 note: data preset inputs (p0p7) are adon't careso while cascade feedback is low. table 2. mode controls (ctl 1 = low, ctl 2 = low, cascade feedback = high) preset inputs divide ratio p7 p6 p5 p4 p3 p2 p1 p0 zero detect q comments 0 0 0 0 0 0 0 0 256 256 max count 0 0 0 0 0 0 0 1 x x illegal state 0 0 0 0 0 0 1 0 2 x min count 0 0 0 0 0 0 1 1 3 x x x x 0 0 0 0 1 1 1 1 15 x 0 0 0 1 0 0 0 0 16 x x x x 0 0 1 0 0 0 0 0 32 x x x x 0 1 0 0 0 0 0 0 64 x x x x 0 1 1 1 1 1 1 1 127 x 1 0 0 0 0 0 0 0 128 128 q output active 1 0 0 0 1 0 0 0 136 136 1 1 1 1 1 1 1 1 255 255 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 128 64 32 16 8 4 2 1 bit value counter #2 binary counter #1 binary counting sequence x = no output (always low)
mc14569b http://onsemi.com 8 table 3. mode controls (ctl 1 = high, ctl 2 = low, cascade feedback = high) preset inputs divide ratio p7 p6 p5 p4 p3 p2 p1 p0 zero detect q comments 0 0 0 0 0 0 0 0 160 160 max count 0 0 0 0 0 0 0 1 x x illegal state 0 0 0 0 0 0 1 0 2 x min count 0 0 0 0 0 0 1 1 3 x x x x 0 0 0 0 1 0 0 1 9 x 0 0 0 1 0 0 0 0 10 x x x x 0 0 0 1 1 0 0 1 19 x 0 0 1 0 0 0 0 0 20 x x x x 0 0 1 1 0 0 0 0 30 x x x x 0 1 0 0 0 0 0 0 40 x x x x 0 1 0 1 0 0 0 0 50 x x x x 0 1 1 0 0 0 0 0 60 x x x x 0 1 1 1 0 0 0 0 70 x x x x 1 0 0 0 0 0 0 0 80 80 q output active 1 0 0 1 0 0 0 0 90 90 1 1 1 1 0 0 0 0 150 150 1 1 1 1 1 0 0 1 159 159 80 40 20 10 8 4 2 1 bit value counter #2 binary counter #1 bcd counting sequence x = no output (always low)
mc14569b http://onsemi.com 9 table 4. mode controls (ctl 1 = low, ctl 2 = high, cascade feedback = high) preset values divide ratio p7 p6 p5 p4 p3 p2 p1 p0 zero detect q comments 0 0 0 0 0 0 0 0 160 160 max count 0 0 0 0 0 0 0 1 x x illegal state 0 0 0 0 0 0 1 0 2 x min count 0 0 0 0 0 0 1 1 3 x x x x 0 0 0 0 1 1 1 1 15 x 0 0 0 1 0 0 0 0 16 x x x x 0 0 0 1 1 1 1 1 31 x 0 0 1 0 0 0 0 0 32 x x x x 0 0 1 1 0 0 0 0 48 x 0 1 0 0 0 0 0 0 64 x 0 1 0 1 0 0 0 0 80 x 0 1 1 1 0 0 0 0 112 x 1 0 0 0 0 0 0 0 128 128 q output active 1 0 0 1 0 0 0 0 144 144 1 0 0 1 1 1 1 1 159 159 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 128 64 32 16 8 4 2 1 bit value counter #2 bcd counter #1 binary counting sequence x = no output (always low)
mc14569b http://onsemi.com 10 table 5. mode controls (ctl 1 = high, ctl 2 = high, cascade feedback = high) preset values divide ratio p7 p6 p5 p4 p3 p2 p1 p0 zero detect q comments 0 0 0 0 0 0 0 0 100 100 max count 0 0 0 0 0 0 0 1 x x illegal state 0 0 0 0 0 0 1 0 2 x min count 0 0 0 0 0 0 1 1 3 x x x x 0 0 0 0 1 0 0 1 9 x 0 0 0 1 0 0 0 0 10 x x x x 0 0 1 1 0 0 0 0 30 x x x x 0 1 0 0 0 0 0 0 40 x x x x 0 1 0 1 0 0 0 0 50 x x x x 0 1 1 1 0 0 0 0 70 x x x x 1 0 0 0 0 0 0 0 80 80 q output active 1 0 0 1 0 0 0 0 90 90 1 0 0 1 1 0 0 1 99 99 80 40 20 10 8 4 2 1 bit value counter #2 bcd counter #1 bcd counting sequence x = no output (always low) timing diagram mc14569b clock 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 divide by 2 divide by 3 divide by 4 divide by 12 zero detect output
mc14569b http://onsemi.com 11 logic diagram q d pe c d p q d pe c d p q d pe c d p q d pe c d p q d pe c d p q d pe c d p q d pe c d p q d pe c d p v dd 1 15 zero detect v dd d qpe d p c d qpe d p c d qpe d p c d qpe d p c iu 2 cascade feedback 7 3 4 5 6 9 11 14 10 12 13 ctl 2 ctl 1 p0 p1 p2 p3 clock p4 p5 p6 p7
mc14569b http://onsemi.com 12 typical applications figure 3. cascading mc14568b and mc14522b or mc14526b with mc14569b f in cf c mc14569b zero detect cf c mc14522b or mc14526b q4 pe 0" cf c mc14522b or mc14526b q4 pe 0" q1/c2 pe 0" mc14568b lsd msd f out dp0 - - - - - - dp3 dp0 - - - - - - dp3 dp0 - - - - - - dp3 q figure 4. frequency synthesizer with mc14568b and mc14569b using a mixer (channel spacing 10 khz) frequencies shown in parenthesis are given as an example (40 khz) v ss pe dp0 - - - - dp3 pc in c1 ct1 0" pc out g f q1/c2 v ss v ss vco f out (144 - 146 mhz) v dd mc14011 cf q zero detect c crystal oscillator 2 k 2 m mixer mc14569b (143.5 mhz)
mc14569b http://onsemi.com 13 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc14569b http://onsemi.com 14 package dimensions tssop16 dt suffix plastic tssop package case 948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n
mc14569b http://onsemi.com 15 package dimensions soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14569b http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14569b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk

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